Mori Ohara

Title

Deputy Director, IBM Research Tokyo, Distinguished Engineer, Chief SW Engineer for Hybrid Cloud on IBM HW

Mori Ohara

Bio

Moriyoshi Ohara's research interests span across software technologies to take advantage of differentiating hardware features, such as confidential computing and hardware acceleration for AI foundation models.

He received a Ph.D. degree in Electrical Engineering from Stanford University in 1996 and is a Senior Member of Association for Computing Machinery (ACM).

Publications

Accelerating Spark Datasets by Inlining Deserialization
- - Jan Wroblewski
  - Kazuaki Ishizaki
  - et al.
- 2017
- IPDPS 2017
Container management as emerging workload for operating systems
- - Tatsushi Inagaki
  - Yohei Ueda
  - et al.
- 2016
- IISWC 2016
Workload characterization for microservices
- - Takanori Ueda
  - Takuya Nakaike
  - et al.
- 2016
- IISWC 2016
Re-constructing high-level information for language-specific binary re-optimization
- - Toshihiko Koju
  - Reid Copeland
  - et al.
- 2016
- CGO 2016
Characterization of call-graph profiles in Java workloads
- - Takuya Nakaike
  - Hiroshi Inoue
  - et al.
- 2014
- IISWC 2014
Scaling analytics applications with OpenCL for loosely coupled heterogeneous clusters
- - Toshio Suganuma
  - Rajaram B. Krishnamurthy
  - et al.
- 2013
- CF 2013
Optimizing indirect branches in a system-level dynamic binary translator
- - Toshihiko Koju
  - Xin Tong
  - et al.
- 2012
- SYSTOR 2012
Aggregating REST requests to accelerate Web 2.0 applications
- - Moriyoshi Ohara
- 2010
- IBM J. Res. Dev
The data-centricity of web 2.0 workloads and its impact on server performance
- - Moriyoshi Ohara
  - Priya Nagpurkar
  - et al.
- 2009
- ISPASS 2009
Real-time mutual-information-based linear registration on the cell broadband engine processor
- - Moriyoshi Ohara
  - Hangu Yeo
  - et al.
- 2007
- ISBI 2007

Patents

- 09 Jul 2013
- US
- 8484423
Method For Controlling Cache
- 28 Jun 2013
- JP
- 5300005
A Method Of Reducing The Waiting Time To Acquire A Lock By Executing A Critical Section On A High-speed Core On Heterogeneous Multi-core Processors
- 24 Jan 2013
- JP
- 5181183
Converter, Server System, Conversion Method And Program
- 18 Sep 2012
- US
- 8271994
Reduced Data Transfer During Processor Context Switching
- 11 Sep 2012
- US
- 8266627
Reduced Data Transfer During Processor Context Switching
- 03 Apr 2012
- US
- 8150852
Converter, Server System, Conversion Method And Program
- 29 Jun 2011
- CN
- ZL200710144162.2
Data Processing Apparatus, Data Processing Method And Program
- 24 Jun 2011
- JP
- 4768054
Method For Controlling Cache
- 17 Jun 2011
- JP
- 4763586
Data Processing Apparatus, Data Processing Method And Program
- 04 Jan 2011
- US
- 7864081
Fast Implementation Of Decoding Function For Variable Length Encoding

Projects

Systems Research in Tokyo

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Top collaborators

KI

Kazuaki Ishizaki

Kazuaki Ishizaki

Senior Technical Staff Member, Research

SV

Swagath Venkataramani

Swagath Venkataramani

Principal Research Scientist, AIU Architecture and Compilers

HI

Hiroshi Inoue

Hiroshi Inoue

Research Staff Member

YU

Yohei Ueda

Yohei Ueda

Staff Research Scientist