40 Gbit/s limiting output buffer in 80 nm CMOS

Abstract

A 40 Gbit/s 1V limiting output buffer for an AC-coupled 50 Ω load with a differential output swing of 660 mV and a gain of 18 dB is presented. A power consumption of only 24 mW and a simulated risetime of 11 ps are achieved by means of a systematic buffer optimisation. © IEE 2005.