George Cheroff, Dale L. Critchlow, et al.
IEEE JSSC
Paper
A 1 mV MOS Comparator
Abstract
An MOS comparator circuit capable of detecting difference signals as low as 1 mV in 3 µs has been designed, built, and tested. The circuit does not require high accuracy components or tight control of device parameter tolerances. © 1978, IEEE. All rights reserved.
Related
Conference paper
Low cost electronic serial memories
Lewis M. Terman, Dennis D. Buss
ISSCC 1977
Conference paper
Taking technology into manufacturing: The limiting step
Andrew S. Grove, Lewis M. Terman
ISSCC 1975
Conference paper
CCD memory using multilevel storage
Lewis M. Terman, Yen S. Yee, et al.
ISSCC 1981