Stefano Bianchi, Irene Muñoz-Martín, et al.
VLSI Circuits 2019
The IBM Power Block is a high power density, low cost 48 V input DC-DC converter, designed to source up to 107 A of continuous output current to processors in high performance computing (HPC) and datacenter servers. Peak efficiency for a 0.75 V output is 90.6% at 45 A and 85.1% at 107 A. An active clamp forward converter (ACFC) architecture uses a pair of primary FETs and a pair of secondary FETs, separated by a planar transformer. A custom timing chip provides four gate timing signals, whose delays can be stored in internal fuses or set through a serial interface. Transformer and inductor magnetics are integrated into a single ferrite structure that allows induced electro motive forces (EMFs) to cancel, thereby providing near zero output current ripple at 0.75 V and low ripple 0.5 V to 1.0 V. Designed for 1 U servers, the Power Block has a 13 mm x 16 mm footprint and a 19 mm height. The electrical output contact's flat top permits mounting a heat sink or cold plate.
Stefano Bianchi, Irene Muñoz-Martín, et al.
VLSI Circuits 2019
Xin Zhang, Andrew Ferencz, et al.
APEC 2017
Gheorghe Almasi, Sameh Asaad, et al.
IBM J. Res. Dev
Paul N. Whatmough, Saekyu Lee, et al.
VLSI Circuits 2019