FPGA-based coprocessor for text string extraction
N.K. Ratha, A.K. Jain, et al.
Workshop CAMP 2000
Affine Control Loops (ACLs) occur frequently in data- and computeintensive applications. Implementing ACLs directly on dedicated hardware has the potential for spectacular performance improvement in area, time and energy. An important challenge for such direct hardware compilation of ACLs is the interconnection between the different processing elements, which may be non-local as well as dynamic. We propose a generic, reconfigurable interconnection fabric which can realize the data-path of any ACL and be dynamically reconfigured in constant time. We have applied for a patent for this technology. © 2008 ACM.
N.K. Ratha, A.K. Jain, et al.
Workshop CAMP 2000
Apostol Natsev, Alexander Haubold, et al.
MMSP 2007
Minkyong Kim, Zhen Liu, et al.
INFOCOM 2008
Arun Viswanathan, Nancy Feldman, et al.
IEEE Communications Magazine