Pablo Fuentes, Mariano Benito, et al.
CCPE
Paper
A four-terabit packet switch supporting long round-trip times
Abstract
A four-terabit packet switch supporting long round-trip times is described. The switch uses a combined input- and crosspoint-queued structure with virtual output queuing at the ingress. The system is build from four different CMOS ASIC building blocks, using a total of 40 chips for the switching core and 64 fabric interface chips on the line cards. Benefits include high scalability, thoroughput and quality of service.
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