Conference paper
Randomizing task placement does not randomize traffic (enough)
Ana Jokanovic, Bogdan Prisacari, et al.
INA-OCMC 2013
A four-terabit packet switch supporting long round-trip times is described. The switch uses a combined input- and crosspoint-queued structure with virtual output queuing at the ingress. The system is build from four different CMOS ASIC building blocks, using a total of 40 chips for the switching core and 64 fabric interface chips on the line cards. Benefits include high scalability, thoroughput and quality of service.
Ana Jokanovic, Bogdan Prisacari, et al.
INA-OCMC 2013
François Abel, Cyriel Minkenberg, et al.
IEEE/ACM Transactions on Networking
Ronald P. Luijten, Ton Engbersen, et al.
ISCAS 2001
H.J.S. Dorren, P. Duan, et al.
ICTON 2011