A low latency and low power dynamic carry save adder

Abstract

This paper presents a 4-to-2 Carry Save Adder (CSA) using dynamic logic and the Limited Switch Dynamic Logic (LSDL) circuit family. Adders are a crucial portion of all floating-point units, since they form the base element of all arithmetic functions. The 4-to-2 ciruits reported previously do not meet the requirements of the next generation of processors. The adder presented here is built using a dynamic circuit style that improves performance significantly. Further a latching element after each dynamic evaluation node controls the power of the dynamic circuits. In this paper we project some of the salient features of the LSDL circuit family by comparing this 4-2 circuit with the most similar static implementation. Use of the LSDL circuit family displays significant improvement not only in terms of performance but also with respect to power dissipation, leakage and area.