Stable SRAM cell design for the 32 nm node and beyond
Leland Chang, David M. Fried, et al.
VLSI Technology 2005
In this work, a switched-capacitor voltage regulator (SCVR) that dithers flying capacitance to reduce output voltage ripple is presented, and the benefits of such ripple reduction are investigated. In the proposed technique, SC converters are designed to run at the maximum available frequency, and the flying capacitance for different phases is adjusted according to load current change through comparators and a digital controller. The proposed technique is demonstrated in a 65 nm test chip consisting of a 40-phase SCVR with 4b capacitance modulation (CM) and a 2 conversion ratio. On-chip circuits for ripple measurement and load performance monitoring were included to accurately assess the magnitude and impact of ripple reduction. Measurement results show that at a 2.3 V input, an on-chip ripple magnitude of 6-16 mV at 1 V output is achieved for 11-142 mA load. Peak efficiency is 70.8% at a power density of 0.187 W/mm2.
Leland Chang, David M. Fried, et al.
VLSI Technology 2005
David J. Frank, Leland Chang, et al.
IEDM 2011
Gokul Krishnan, Zhenyu Wang, et al.
ICSICT 2022
Suyoung Bang, Jae-Sun Seo, et al.
VLSI Circuits 2015