C. Eric Wu, Anthony Bolmarcich
ICPADS 2002
Parallel accesses to the table lookaside buffer (TLB) and cache array are crucial for high-performance computer systems, and the choice of cache types is one of the most important factors affecting cache performance. In this paper we classify caches according to both index and tag. Since both index and tag could be either virtual (V) or real (R), our classification results in four combinations or cache types. The real address caches with virtual tags for high-performance computer systems in our study are prediction-based, since index bins are generated from a small array and predictions could be false. As a result, we also discuss and evaluate real address MRU caches with real tags, and propose virtually indexed MRU caches with real tags. Each of the four cache types and MRU caches are discussed and evaluated using trace-driven simulation. Our results show that a virtually indexed MRU cache with real tags is a good choice for high-performance computer systems. © 1993 IEEE
C. Eric Wu, Anthony Bolmarcich
ICPADS 2002
Dan Williams, Hakim Weatherspoon, et al.
VEE 2011
Yew-Huey Liu, Jun-Jang Jeng
ICEBE 2007
Vivek Shrivastava, Petros Zerfos, et al.
INFOCOM 2011