Workshop paper
Flow: A stream processing system simulator
Alfred J Park, Cheng-Hong Li, et al.
HOTI 2010
In the synthesis of digital circuits, one encounters the problem of identifying blocks which have been designed, so that there is no replication in the expensive effort of generating the physical layout of these blocks. We present a model for the synthesis of combinational logic into complex MOS circuits and present a ranking and unranking procedure to characterize the layout of each complex MOS circuit. © 1987 IEEE
Alfred J Park, Cheng-Hong Li, et al.
HOTI 2010
Ravi Nair
Proceedings of the IEEE
Lakshminarayanan Renganarayana, Vijayalakshmi Srinivasan, et al.
SPLASH 2012
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CF 2015