Daniel L. Ostapko, June Hong Se
IEEE TC
Paper
A Simple Procedure to Generate Optimum Test Patterns for Parity Logic Networks
Abstract
A simple procedure to produce a minimum length test set for a parity network is presented. If is the largest fan in of any EX-OR gate element in the tree, 2M test patterns are chosen by considering only 2M test sequences, of length 2M, assigned to each signal line. Copyright © 1981 by The Institute of Electrical and Electronics Engineers, Inc.
Related
Chidanand Apte, Se June Hong, et al.
Intelligent Data Analysis
Se June Hong
IEEE Transactions on Knowledge and Data Engineering
David Waltz, Se June Hong
IEEE Intelligent Systems and Their Applications