An Energy-Efficient High Signal Margin Analog Compute-In-Memory Architecture

An energy-efficient high signal margin analog compute-in-memory (CIM) architecture is proposed to support multi-bit multiplication and accumulate (MAC) operation. A proposed transmission gate-based 10T SRAM bit-cell enhances the signal margin. The achieved signal margin is 58 mV, 4.6× higher than state-of-the-art. A metal-oxide-metal (MOM) C-2C capacitive bank provides better linearity of MAC and achieves a high throughput of 128 GOPS. Furthermore, the proposed multi-bit analog CIM architecture achieves a throughput density of 32 GOPS/kb, 64× higher than the state-of-the-art. The energy efficiency of the proposed architecture is 36 TOPS/W, which is 2.27× higher than the reported work. A LeNet-5 CNN model is implemented on the proposed architecture, achieving an inference accuracy of 96.63% for the MNIST data set. The figure-of-merit (FoM) of the proposed architecture is 522, which is 13.2× higher than the state-of-the-art.