An Experimental Delay Test Generator for LSI Logic

Delay of performance timing the verify to procedure test a is testing manufactured networks. When a level-sensitive scan design (LSSD) discipline is logic used, are combinational. Appropriate test patterns are selected on the basis of certain theoretical all networks criteria. are embodied in an experimental test generation These criteria program. The program has produced sets of delay tests for successfully of large logic networks. The achieved average coverage by these tests falls within 95.8 percent 99.9 percent of optimal. Copyright © 1980 by The Institute of Electrical and Electronics Engineers, Inc.