Ziyang Liu, Sivaramakrishnan Natarajan, et al.
VLDB
As one of the most highly integrated system-on-a-chip application-specific integrated circuits (ASICs) to date, the Blue Gene®/L compute chip presented unique challenges that required extensions of the standard ASIC synthesis, timing, and physical design methodologies. We describe the design flow from floorplanning through synthesis and timing closure to physical design, with emphasis on the novel features of this ASIC. Among these are a process to easily inject datapath placements for speed-critical circuits or to relieve wire congestion, and a timing closure methodology that resulted in timing closure for both nominal and worst-case timing specifications. The physical design methodology featured removal of the pre-physical-design buffering to improve routability and visualization of buses, and it featured strategic seeding of buffers to close wiring and timing and end up at 90% utilization of total chip area. Robustness was enhanced by using additional input/output (I/O) and internal decoupling capacitors and by increasing I/O-to-C4 wire widths. © Copyright 2005 by International Business Machines Corporation.
Ziyang Liu, Sivaramakrishnan Natarajan, et al.
VLDB
Kafai Lai, Alan E. Rosenbluth, et al.
SPIE Advanced Lithography 2007
William Hinsberg, Joy Cheng, et al.
SPIE Advanced Lithography 2010
Arun Viswanathan, Nancy Feldman, et al.
IEEE Communications Magazine