Performance test case generation for microprocessors
Pradip Bose
VTS 1998
Next generation cognitive radio networks require an RF and mixed signal hardware architecture that can achieve low-energy, very wideband spectrum sensing. We survey state-of-the-art low-power CMOS building blocks as potential candidates for realizing such an architecture. For the critical analog-to-digital converter, we compare time-interleaved and frequency-interleaved architectures, including system-level simulations, and frequency-interleaving is shown to provide significant advantages. Measurement results from a 3.8 mW 5 GHz bandwidth analog domain frequency interleaver are presented to confirm the possibility of a very low-energy frequency domain digitizer. Coupled with DSP for calibration and signal feature extraction, this architecture has significant promise for cognitive spectrum sensing. Copyright © 2014 IEEE.
Pradip Bose
VTS 1998
Maurice Hanan, Peter K. Wolff, et al.
DAC 1976
Lixi Zhou, Jiaqing Chen, et al.
VLDB
Elliot Linzer, M. Vetterli
Computing