Conference paper
Parallel logic/fault simulation of VLSI array logic
Pradip Bose
ICCAD 1987
The present methodology for designing state-of-the-art microprocessors involves modeling at various levels of abstraction. Currently, there is a need for better integration between the modeling and validation methodologies. In this report, an account is given on some of the innovative leading-edge technologies in academia and industry.
Pradip Bose
ICCAD 1987
A.-T. Nguyen, Pradip Bose, et al.
IPPS 1997
Pradip Bose
ICCD 1985
A.-T. Nguyen, J.-D. Wellman, et al.
HPCC 1997