Chip to carrier C4 technology challenges with Pb-free solders

Abstract

IBM's C4 interconnection technology has continuously evolved over a period of forty years, i.e. from evaporation, to electroplating to C4NP, a C4 New Process. IBM's initial C4NP efforts are focused on Sn-based Pb-free solder technology, in line with client requirements. Currently, all IBM bumped lead-free C4s are produced using the C4NP technology. Sn-based lead-free solders pose unique challenges because of higher microhardness and anisotropy of the tin crystalline structure, as compared to Pb-based solders. The simultaneous design requirements of increased power and current density, increased I/O counts and larger chips, and weak BEOL structure with low-k or ultra-low-k dielectric, demand a careful material interaction optimization between under bump metallurgy (UBM), bump solder, laminate solder, and laminate surface finish. In this paper, we will be discussing the challenges and some solutions of lead-free C4 bumping in terms of mechanical and thermo-electromigration. © 2008 IEEE.