Metal-Clad InP Cavities for Nanolasers on Si
Preksha Tiwari, Svenja Mauthe, et al.
IPC 2020
We demonstrate for the first time a technology which allows the monolithic integration of both p-Type (InAs-Si) and n-Type (InAs-GaSb) heterojunction Tunnel FETs (TFET) laterally on a Si substrate. The lateral heterojunction nanowire (NW) structures are implemented using top-down CMOS-compatible processes combined with Template-Assisted Selective Epitaxy (TASE) [1] of the III-V materials. Sub-40nm InAs-Si p-TFETs and InAs-GaSb n-TFETs have been fabricated and represent to the best of our knowledge the first lateral III-V heterostructure NW TFETs. The InAs-Si p-TFETs show excellent performance with average subthreshold swing, SSave, of ∼70mV/dec. combined with an on-current, Ion, of 4μA/μm at VDS = VGS =-0.5V. The InAs-GaSb n-TFETs have about an order of magnitude higher Ion, but SS is deteriorated due to high interface traps density (Dit).
Preksha Tiwari, Svenja Mauthe, et al.
IPC 2020
Heinz Schmid, Hans Biebuyck, et al.
Journal of Vacuum Science and Technology B: Microelectronics and Nanometer Structures
M. Scherrer, S. Kim, et al.
SPIE Nanoscience + Engineering 2021
Noelia Vico Triviño, Philipp Staudinger, et al.
PVLED 2019