David Brooks, Pradip Bose, et al.
IBM J. Res. Dev
We present a new design in which two branch prediction mechanisms are used in conjunction. We show that the combination of these mechanisms will reduce branch penalty, while also reducing chip area. © 1992.
David Brooks, Pradip Bose, et al.
IBM J. Res. Dev
Alan M. Webb, Ray Mansell, et al.
IBM J. Res. Dev
Philip G. Emma
IEEE Micro
Philip G. Emma
IEEE Micro