Copper ULSI interconnect technology

Abstract

Recently IBM announced the first implementation of full copper ULSI wiring in a CMOS technology, to be manufactured on its high-performance 0.22 μm CMOS products this year. Features of this technology will be presented, as well as functional verification on CMOS chips. To reach this level, extensive yield, reliability, and stress testing had to be done on test and product-like chips, including those packaged into product modules. Data will be presented from all aspects of this testing, ranging from experiments designed to promote Cu contamination of the MOS devices, to temperature/humidity/bias stressing of assembled functional modules. The results in all areas are shown to be equal to or better than standards set by our current Al(Cu)/W-stud technology. This demonstrates that the potential problems associated with copper wiring that have long been discussed can be overcome.