Cryogenic CMOS Circuits for Future Scaled Quantum Computing Systems: Challenges and Solutions

Quantum computers offer the promise of accelerated solutions for types of problems that are computationally unaffordable or intractable for classical computers, such as the simulation of quantum mechanics itself, quantum chemistry, and mathematical challenges like factoring large numbers. However, the relatively high error rate per quantum computing operation in the systems of today and of those expected to be developed in the future remains a key obstacle. To address this challenge, quantum error correction (QEC), which enables the creation of error-corrected (logical) qubits from a collection of physical qubits, is required. Depending on the choice of QEC code, hundreds of physical qubits may be required to implement a single logical qubit. As a result, the race to the creation of quantum computing systems capable of outperforming classical computing systems is largely a race to create quantum computers at the scale needed to support QEC. The criticality of scaling is evident in the quantum computing roadmaps produced by major research labs in this field, such as the one from IBM shown in Fig. 1. Starting from systems with only a few physical qubits a few years ago, the roadmap projects quantum computers with around 100,000 physical qubits and thousands of logical qubits by 2033 or so.