Cycle-accurate replay and debugging of running FPGA systems

Abstract

Finding bugs in software that are timing dependent or caused by non-deterministic inputs is notoriously difficult. In FPGAs, the problem is much worse because the visibility into the running design tends to be very low, and existing tools either gather too little data for diagnosis, or are so intrusive that they perturb the timing and may mask the bug. This leads to long FPGA development cycles, and is exacerbated by the steady increase in complexity of FPGA designs. We present a tool - Panoptic on - that logs data and timing information at key design points, extracts it from the FPGA, and uses it for cycle-accurate replay of the entire execution in simulation. This allows interactive debugging with full visibility into the design.