Global routing revisited
Michael D. Moffitt
ICCAD 2009
In this paper, we discuss the microarchitecture, design, and verification of two IBM System z10™ I/O (input/output) chips: the z10™ hub chip, an In.niBand™ host channel adapter with IBM-proprietary enhancements, and the InfiniBand memory bus adapter (MBA) chip, an InfiniBand-to-self-timed-interface fanout chip for attaching legacy I/O. Designing and verifying these chips presented many challenges. We describe our transaction- and packet-tracking concepts and the use of communication groups that emulate the behavior of logical partitions and their role in handling error and recovery cases. A novel technique has been employed to ensure that design implementation and architectural register definitions are consistent in a fully automated approach. Finally, we describe our approach to improving self-test coverage, which is based on an automated process of test-point insertion. © Copyright 2009 by International Business Machines Corporation.
Michael D. Moffitt
ICCAD 2009
S.F. Fan, W.B. Yun, et al.
Proceedings of SPIE 1989
Robert C. Durbeck
IEEE TACON
Thomas M. Cover
IEEE Trans. Inf. Theory