David Demaris, Maria Gabrani, et al.
SPIE Advanced Lithography 2012
We present a design methodology for a modular network processor architecture that leads to a balanced, service-defined mix between programmable processor cores, configurable hardware assists, and specialized coprocessors. Whereas the processor cores address the flexibility and extendibility needs of the networking market, the hardware components offload the processors, or even allow them to be bypassed for certain network processor-typical tasks to optimize chip area, performance, and power efficiency. We describe the rationale behind the selected functional partitioning in hardware and software components and discuss the challenges of designing the hardware components, and of organizing and integrating the programmable cores. We quantify our approach with a performance evaluation of the overall system. © 2003 Published by Elsevier Science B.V.
David Demaris, Maria Gabrani, et al.
SPIE Advanced Lithography 2012
F. De Morsier, David Demaris, et al.
SPIE Advanced Lithography 2014
Antonio Foncubierta-Rodriguez, Anca Nicoleta Ciubotaru, et al.
GREC 2017
Aditya Kashyap, Anna Fomitcheva Khartchenko, et al.
Nature Biomedical Engineering