Design of a dynamic memory access scheduler

Abstract

Computer systems are becoming increasingly limited by memory performance. A dynamic SDRAM access scheduler (DSAS) according to modern SDRAM technology and memory access scheduling algorithms is proposed in this paper. Based on SDR-SDRAM technology and new version AMBA AXI bus, DSAS dynamically schedules the accesses to SDRAM and reduces precharge time. A modularized configurable automatic verification platform is established to verify basic functions of DSAS. We analyze the results and conclude that the memory controller using DSAS is capable of predicting future operations, thus greatly hide the precharge time, which takes much time in SDRAM operations; AXI bus throughput rate has improved by 19%∼52% during frequent SDRAM accesses. © 2007 IEEE.