Design of a Wide-Loading-Range Cap-Less LDO With Enhanced Power Supply Rejection and Speed

This paper introduces an output Capacitor-Less (Cap-Less) Low-Drop-Out regulator (LDO) design with NMOS pass-transistor, featuring a wide loading range with enhanced power supply rejection (PSR) and transient response. From small-signal perspective, the proposed dual-loop design achieves up to 44.6-MHz bandwidth at heavy load while maintaining stability across the full loading range from 0.1 mA to 300 mA by the adaptive biasing and zero compensation techniques. From large-signal perspective, the proposed NMOS Super Source Follower (N-SSF) and small- and large-signal conflict softening filter also enhance the slew-rate for faster transient response. The proposed design is presented with bottom-up considerations and then with overall system analysis. Measurement in 180-nm CMOS shows only an 18-mV undershoot with on-chip 1 mA to 272 mA load transient steps in 100 ns with a 50-pF on-chip output capacitance. At 10 MHz, a measured PSR better than -30 dB was also observed from 1-mA and 100-mA loading currents.