Conference paper
Control store implementation of a high performance VLSI CISC
J.H. Chang, H.H. Chao, et al.
MICRO Annual Workshop 1987
A global optimization scheme for control circuit design using programmable logic array (PLA) implementation is presented. The control circuit is optimized with respect to performance, power, and area, as well as design effort through interactive logic, circuit, and layout designs. The optimization scheme has been successfully applied in the design of the execution unit control and the bus controller of a 32-bit microprocessor. The tradeoffs of various design approaches are discussed.
J.H. Chang, H.H. Chao, et al.
MICRO Annual Workshop 1987
F.Warren Shih, Tze-Chiang Lee, et al.
ICCD 1990
Pradip Bose
ICCD 1985
F.Warren Shih, H.H. Chao, et al.
IEEE ITC 1985