DiffChip: Thermally Aware Chip Placement with Automatic Differentiation

Chiplets are small, modular integrated circuits that can be combined to form a larger system, offering flexibility and performance enhancements. However, their dense packing and close proximity often lead to significant thermal management challenges, requiring careful floor planning to ensure efficient heat distribution. To address thermal considerations, floor-planning algorithms concurrently minimize the total wirelength and the maximum temperature. However, these efforts employ gradient-free approaches, such as simulated annealing, which suffer from poor scaling and slow convergence. In this paper, we propose Diffchip, a chiplet placement algorithm based on automatic differentiation (AD). The proposed framework relies on a differentiable thermal solver that computes the sensitivity of the temperature map with respect to the chiplet's location. Regularization strategies for peak temperature, heat sources, and material properties enable end-to-end differentiability, allowing for gradient-based optimization. This feature, together with a novel differentiable non-overlap constraint, enables us to quickly identify the chiplets' arrangement that minimizes the wirelength while keeping the maximum temperature within a desired threshold. In the experiments presented, our framework decreased the maximum temperature by approximately 10 °C in under 15 iterations. The optimized layout is validated with commercial software. Leveraging modern AD frameworks and physics-aware optimization, our work accelerates the design of microelectronic systems.