Ullrich R. Pfeiffer, Scott K. Reynolds, et al.
RFIC 2004
This paper presents 8-tap and 10-tap, 6-b filters designed to provide PR-IV channel equalization at data rates in excess of 20 megabyte/s. Achieving high sampling rates while reducing power and area required an optimized distributed-arithmetic (DA) architecture combined with custom circuit design and layout. These filters improve attainable data rate by 40% while reducing macro area by 20% compared with standard-cell-designed filters using the same architecture and technology. © 1995 IEEE
Ullrich R. Pfeiffer, Scott K. Reynolds, et al.
RFIC 2004
John J. Pekarik, Jim Adkisson, et al.
BCTM 2014
Scott K. Reynolds, Arun S. Natarajan, et al.
RFIC 2010
Scott K. Reynolds, Christopher J. Smart, et al.
Applied Physics Letters