Vittorio Castelli, Lawrence Bergman
IUI 2007
A high bandwidth critical path monitor (1 sample/cycle at 4-5 GHz) capable of providing real-time timing margin information to a variable voltage/frequency scaling control loop is described. The critical path monitor tracks the critical path delay to within 1 FO2 inverter delay with a standard deviation less than 3 FO2 delays over process, voltage, temperature, and workload. The CPM is sensitive to 20mV/bit A/C and 10mV/bit DC voltage changes, and less than 10°C/bit temperature changes.
Vittorio Castelli, Lawrence Bergman
IUI 2007
Michael Heck, Masayuki Suzuki, et al.
INTERSPEECH 2017
Fan Zhang, Junwei Cao, et al.
IEEE TETC
Jean McKendree, John M. Carroll
CHI 1986