Enablement of variation-aware timing: Treatment of parasitic resistance and capacitance

Abstract

We describe our enablement of variation-aware timing for ASIC circuits at the 90 nm CMOS technology node. In particular, we focus on the enablement of statistical process variations in parasitic resistance and capacitance at the Spice model level, which is an industry first. Traditional layout-to-Spice- netlist parasitic extraction (PEX) tools create resistor elements and capacitor elements with fixed values for parasitic resistance (R) and capacitance (C) in interconnect and in circuits. As such, the statistical variations in parasitic R and C are lost. Our enablement suite, which includes both a layout-to-Spice-netlist PEX tool and Spice models, supports not only the nominal values of parasitic R and C, but also provides the lower and upper bounds of parasitic R and C. More importantly, these lower and upper bounds and their nominal R and C values are in the same netlist, so that the continuous skewing of parasitic R and C is enabled. This is our first innovation. Our second innovation is to enable the Monte Carlo simulations of parasitic R and C. Our third innovation is to distinguish parasitic R and C from different interconnect levels or from poly, diffusion, substrate, and provides an independent skewing parameter for each metal level, via level, poly, diffusion, substrate, etc. We also explain how to do skewing/corner modeling for parasitic R and C. © 2007 IEEE.