Fabrication and performance limits of sub-0.1 μm Cu interconnects

Abstract

As the on-chip interconnect linewidth and film thickness shrink below 0.1 μm, the size effect on Cu resistivity becomes important, and the electrical performance deliverable by such narrow metal lines needs to be assessed critically. From the fabrication viewpoint, it is also crucial to determine how structural parameters affect resistivity in the sub-0.1 μm feature size regime. To evaluate the scaling of resistivity with thickness, we have fabricated a series of Ta/Cu/Ta/SiO2 thin film structures with Cu thickness ranging from 1μm to 0.02 μm. These test structures revealed a far larger (∼2.3×) size effect than that expected from surface scattering. We have also fabricated test structures containing 50-nm-wide Cu lines wrapped in Ta-based liners and embedded in insulating SiO2 using e-beam lithography, high-density plasma etching, ionized PVD Cu deposition, and chemical-mechanical planarization processes. Direct current (16 nA) resistance measurements from these 50-nm-wide Cu lines have also shown a higher-than-expected distribution of resistivity. Cross-sectional TEM and surface AFM observations suggest that the observed extra resistivity increase can be attributed to small grain sizes in ultrathin Cu films and to Cu/Ta interface roughness. Monte Carlo simulations are used to quantify the extra resistivity resulting from interface roughness.