Floating body effects in partially-depleted SOI CMOS circuits

Abstract

This paper presents a detailed study on the impact of floating body in partially-depleted (PD) SOI MOS-FET on various digital VLSI CMOS circuit families. The parasitic bipolar effect resulting from the floating body is shown to degrade the circuit noise margin and stability in general. In certain dynamic circuits and wide multiplexers, the parasitic bipolar effect is shown to cause logic state error if not properly accounted for.