Fully monolithic 1.25 GHz CMOS frequency synthesizer

A fully monolithic frequency synthesizer PLL circuit implemented in a 0.45 μm CMOS technology is presented. The test chip consumes 270 mW at 1.25 GHz from a 3.3 V supply. The rms jitter of the generated clock is 1.4 ps. No external components are used except supply decoupling capacitors.