F.R. Gfeller, P. Buchmann, et al.
ISLC 1992
A 10:1 serializer/deserializer subsystem with fast byte synchronisation and link control functions has been designed. The subsystem, consisting of 1030 gates, was implemented on GaAs using a refractory-gate MESFET process and is part of an optoelectronic transmitter/receiver chip set for fibre-optic computer communication links. An operating speed of 1 Gbit/s was achieved with a power dissipation of only 1.2 W.
F.R. Gfeller, P. Buchmann, et al.
ISLC 1992
M.B. Ritter, F.R. Gfeller, et al.
ISSCC 1996
F.R. Gfeller, W. Hirt, et al.
VTC 1996
F.R. Gfeller, D.J. Webb
Journal of Applied Physics