Generation of Stressmarks for Early Stage Soft-Error Modeling

Abstract

Early-stage Soft-Error Rate (SER) vulnerability modeling and estimation is essential for all types of processing platforms, ranging from embedded/IoT processors to server-class systems, to ensure reliable and deterministic operation. The objective of such modeling is to provide inputs to designers on the addition of protection features, such as latch hardening, parity protection, ECC and redundancy techniques, for achieving RAS targets without significantly impacting the overall processor area and power. This calls for a systematic methodology, starting from the latch level and moving up to the micro-architecture and architecture level of abstraction. In this paper, we present a methodology that characterizes processor vulnerability and define a metric to effectively quantify this vulnerability. Based on these characterizations, we propose techniques to generate synthetic stressmarks that maximize SER vulnerability for a given processor configuration. We carry out an exploration of these stressmarks across different operating corners for a state-of-the-art POWERTM ISA-based server-class processor. In comparison to single instruction microbenchmarks as well as real workloads from the SPEC-2017 benchmark suite, our stressmarks demonstrate up to 16X increase in vulnerability in terms of our proposed metric.