Triangle Counting and Truss Decomposition using FPGA
Sitao Huang, Mohamed El-Hadedy, et al.
HPEC 2018
As the trends driven by Moore's law come to an end, increased heterogeneity at all levels of computing is required to deliver the computing performance needed for emerging applications, leading to the proliferation of various application- or domain-specific accelerators. This in turn demands more memory bandwidth, as heterogeneous computing with accelerators consumes data at a much higher rate than traditional homogeneous computing, limiting the computing performance. To tackle this challenge, this article presents a conceptual near-memory acceleration architecture; demonstrates its practicality and plausibility using a recent experimental platform from IBM, as well as its potential impact on performance and energy efficiency; and discusses the need for adopting a high-level synthesis approach for such a near-memory acceleration architecture. Subsequently, this article concludes with future research directions for broad adoption of near-memory acceleration.
Sitao Huang, Mohamed El-Hadedy, et al.
HPEC 2018
Vikram Sharma Mailthody, Ketan Date, et al.
HPEC 2018
Abdul Dakkak, Cheng Li, et al.
ICS 2019
Yuhong Li, Cong Hao, et al.
DAC 2020