P. Solomon, C.M. Knoedler, et al.
IEEE T-ED
When linear voltage ramps were applied to MOS capacitors, the current-vs-voltage (I-V) curves indicated a region of quasisaturation of current, i.e., a ledge in the I-V characteristic. These ledges could be explained by an electron-trapping model. Trap cross sections and concentrations were dependent on sample processing and oxide thickness and were in the 10 -19 cm2 and 1012 cm-2 ranges, respectively. Comparison of shifts in the I-V and C-V curves showed that trapped charge to be within about 10 Å of the Si-SiO2 interface.
P. Solomon, C.M. Knoedler, et al.
IEEE T-ED
Y. Kim, S.-C. Seo, et al.
SNW 2021
H.-S. Wong, David J. Franks, et al.
IEDM 1998
E.C. Jones, S. Tiwari, et al.
IEEE International SOI Conference 1998