Seshadri Subbanna, Gregory Freeman, et al.
Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers
Circuit design techniques for realizing high-frequency, low-power phase-locked loops (PLL‘s) in monolithic silicon bipolar technology are discussed. A varactor-tuned voltage-controlled oscillator (VCO), an analog phase detector, and a bandgap reference have been utilized as building blocks. A test circuit fabricated in a 2-µm bipolar process exhibited a maximum center frequency of 350 MHz, and the PLL pull-in range was larger than ± 1 percent. The circuit operates from a 5-V supply and dissipates 270 mW. © 1989 IEEE
Seshadri Subbanna, Gregory Freeman, et al.
Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers
Mehmet Soyuer, Joachim N. Burghartz, et al.
IEEE Journal of Solid-State Circuits
Jean-Olivier Plouchart, Herschel Ainspan, et al.
EuMC 1999
Mehmet Soyuer
IEEE Journal of Solid-State Circuits