A 5.5-GHz low noise amplifier in SiGe BiCMOS
Herschel A. Ainspan, Charles S. Webster, et al.
ESSCIRC 1998
Circuit design techniques for realizing high-frequency, low-power phase-locked loops (PLL‘s) in monolithic silicon bipolar technology are discussed. A varactor-tuned voltage-controlled oscillator (VCO), an analog phase detector, and a bandgap reference have been utilized as building blocks. A test circuit fabricated in a 2-µm bipolar process exhibited a maximum center frequency of 350 MHz, and the PLL pull-in range was larger than ± 1 percent. The circuit operates from a 5-V supply and dissipates 270 mW. © 1989 IEEE
Herschel A. Ainspan, Charles S. Webster, et al.
ESSCIRC 1998
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IEEE JSSC
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VLSI Technology and Circuits 2022
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IEEE T-MTT