High Performance MOS Integrated Circuit Using the Ion Implantation Technique

Abstract

Extensive use has been made of the advantages ion implantation has to offer over standard processing for the fabrication of high performance n-channel MOS circuits. By combining an enhancement driver with a depletion load, the maximum switching speed of FET logic elements has been evaluated for self-aligned structures with various channel lengths and various degrees of substrate decoupling via device-to-substrate capacitances. An 11-stage ring-oscillator circuit is used for performance evaluation. Switching delays as small as 115 ps were obtained for such inverter stages built on 200 Ω. cm substrate material and having l-μm channel length. Essential fabrication details and circuit behaviors are described. Copyright © 1975 by The Institute of Electrical and Electronics Engineers, Inc.