High performance packaging laminates enable buses for exascale systems

Abstract

This paper summarizes the exploratory work conducted at IBM Research, NTK Technologies, and Zeon Corporation, which seeks to expand bandwidth and reduce power consumption of electrical I/O for future exascale computing systems. The development of novel low-loss dielectric materials was coupled with high-speed and power configurable (4-tap FFE/15-tap DFE) circuit designs to achieve 25Gbps per channel data-rate for aggregated parallel buses. In addition, new via structures were utilized in the first-level substrate to mitigate return path discontinuities. Meanwhile, dual layer dielectrics combined with a special manufacturing process allows the use of smooth copper foils to further reduce high frequency losses due to surface roughness. Results from test vehicles confirmed over 20% reduction in channel loss at 20GHz when compared to currently leading commercial materials, which permits the extension of electrical link performance to meet future system requirements.