In-Memory Computing for Deep Learning Inference: An Overview and Future Prospects

Analog in-memory computing (AIMC), where synaptic weights are stored in nanoscale non- volatile memory elements and computations are carried out in the analogue or mixed-signal domain, represents a promising brain-inspired approach for developing the next generation of deep learning accelerators. In the first part of the presentation, I will explore the current advancements in this area, focusing on a 64-core AIMC chip built using 14nm CMOS technology with integrated phase-change memory. This chip achieves classification accuracy comparable to floating-point operations and demonstrates seamless integration of analogue and digital processing units. This work lays the foundation for a heterogeneous mixed-signal architecture. In the second part, I will cover ongoing efforts to design the next generation of AIMC chips for deep learning inference, targeting both edge and cloud domains.