Leon Stok, D.S. Kung, et al.
IBM J. Res. Dev
Paper
Incremental synthesis
Abstract
A small change in the input to logic synthesis may cause a large change in the output implementation. This is undesirable if a designer has some investment in the old implementation and does not want it perturbed more than necessary. We describe a method that solves this problem by reusing gates from the old implementation, and restricting synthesis to the modified portions only.
Related
Conference paper
Synthesis of fully testable sequential machines
R. Thomas, Sandip Kundu
European Conference on Design Automation 1992
Conference paper
Timing analysis and optimization: From devices to systems
A. Devgan, Sandip Kundu
ASP-DAC 1998
Conference paper
A small test generator for large designs
Sandip Kundu, Leendert M. Huisman, et al.
IEEE ITC 1992