Leon Stok, D.S. Kung, et al.
IBM J. Res. Dev
A small change in the input to logic synthesis may cause a large change in the output implementation. This is undesirable if a designer has some investment in the old implementation and does not want it perturbed more than necessary. We describe a method that solves this problem by reusing gates from the old implementation, and restricting synthesis to the modified portions only.
Leon Stok, D.S. Kung, et al.
IBM J. Res. Dev
D. Brand, V.S. Iyengar
ICCAD 1985
D. Brand, Chandramouli Visweswariah
ICCAD 1996
Leonard Berman, Louise Trevillyan, et al.
ISCAS 1987