Conference paper
Timing analysis and optimization: From devices to systems
A. Devgan, Sandip Kundu
ASP-DAC 1998
A small change in the input to logic synthesis may cause a large change in the output implementation. This is undesirable if a designer has some investment in the old implementation and does not want it perturbed more than necessary. We describe a method that solves this problem by reusing gates from the old implementation, and restricting synthesis to the modified portions only.
A. Devgan, Sandip Kundu
ASP-DAC 1998
Sandip Kundu
ICCD 1994
Leon Stok, D.S. Kung, et al.
IBM J. Res. Dev
D. Brand, V.S. Iyengar
ICCAD 1985