Sandip Kundu, E.S. Sogomonyan, et al.
IEEE TC
A small change in the input to logic synthesis may cause a large change in the output implementation. This is undesirable if a designer has some investment in the old implementation and does not want it perturbed more than necessary. We describe a method that solves this problem by reusing gates from the old implementation, and restricting synthesis to the modified portions only.
Sandip Kundu, E.S. Sogomonyan, et al.
IEEE TC
D. Brand
ICCAD 1987
D. Brand, R. Damiano, et al.
ICCD 1994
D. Brand, Chandramouli Visweswariah
ICCAD 1996