J.Z. Sun, M.C. Gaidis, et al.
Applied Physics Letters
Paper
Josephson integrated circuit process for scientific applications
Abstract
We have developed and are regularly practicing a seven mask-level Josephson integrated circuit fabrication process tailored to de SQUID requirements and intended for SQUID studies and other scientific applications of Josephson technology. The process incorporates low capacitance Nb/Nb2O5/PbAuIn. edge junctions, PdAu shunt resistors, and a wiring pitch of 5μm for the SQUID input coil level (which is PbAuIn). The junctions can be made as small as 2μm by 0.3μm, with a capacitance (including parasitics) of ~0.14 pF. This process yields stable and reliable junctions and integrated circuits. © 1987 IEEE.
Related
R.H. Koch, J.Z. Sun, et al.
Applied Physics Letters
V. Foglietti, A. Pasquarelli, et al.
IEEE TAS
R.T. Collins, Z. Schlesinger, et al.
Physical Review Letters