A 1.8V 12-bit 230-MS/s pipeline ADC in 0.18μm CMOS technology
Thomas Liechti, Armin Tajalli, et al.
APCCAS 2008
This work presents the design and the silicon implementation of an on-line energy optimizer unit based on novel analog computation approaches, which is capable of dynamically adjusting power supply voltages and operating frequencies of multiple processing elements on-chip. The optimized voltage/frequency assignments are tailored to the instantaneous workload information on multiple tasks and fully adaptive to variations in process and temperature. The optimizer unit has a response time of less than 50 μs, occupies a silicon area of 0.021 mm2/task and dissipates 2 mW/task. © 2007 IEEE.
Thomas Liechti, Armin Tajalli, et al.
APCCAS 2008
Eric J. Fluhr, Joshua Friedrich, et al.
ISSCC 2014
Timothy O. Dickson, Zeynep Toprak Deniz, et al.
IEEE JSSC
Irem Boybat, Manuel Le Gallo, et al.
NVMTS 2017