On the fundamental design gap in terabit per second packet switching

Abstract

We discuss the gap we experience in an industrial design path of high-speed packet switches. As bandwidth demand exceeds progress in CMOS technology, system architects are forced to abandon familiar design solutions and make fundamental changes to their architectures at an increasingly faster pace. We investigate design methods to decrease the risk of such changes and to provide a structured and confident transition from conceptual system-level models to hardware descriptions. It appears that the design gap is caused by differences between language primitives and underlying concepts of system-level design languages and hardware description languages. We substantiate the need for expressive system-level modeling concepts and show that the gap is actually caused by a fundamental interpretation mismatch between models and descriptions. Based on a comparison of existing system-level synthesis methods with the interpretation gap, we propose to decrease the gap by using modeling patterns.