Shmuel Wimer, Ron Y. Pinter, et al.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Chaining is the ability to pipeline two or more vector instructions on Cray-1 like machines. We show how to optimally use this feature to compute (vector) expression trees, in the context of automatic code-generation. We present a linear-time scheduling algorithm for finding an optimal order of evaluation for a machine with a bounded number of registers. © 1986, ACM. All rights reserved.
Shmuel Wimer, Ron Y. Pinter, et al.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
David Bernstein, Haran Boral, et al.
SIGPLAN Symposium on Compiler Construction 1986
David Bernstein, Haran Boral, et al.
IEEE TC
Amnon Joseph, Ron Y. Pinter
Integration, the VLSI Journal