Optimal P/N width ratio selection for standard cell libraries

Abstract

The effectiveness of logic synthesis of satisfy increasingly tight timing constraints in deep-submicron high-performance circuits heavily depends on the range and variety of logic gates available in the standard cell library. Primarily, research in the design of high-performance standard cell libraries has been focused on drive strength selection of various logic gates. Since CMOS logic circuit delays not only depend on the drive strength of each gate but also on its P/N width ratio, it is crucial to provide good P/N width ratios for each cell. The main contribution of this paper is the development of a theoretical framework through which library designers can determine 'optimal' P/N width ratio for each logic gate in their high-performance standard cell library. This theoretical framework utilizes new gate delay models that explicitly represent the dependence of delay on P/N width ratio and load. These delay models yield highly accurate delay for CMOS gates in a 0.12 μm Leff deep-submicron technology.