Optimal scheduling of signature analysis for VLSI testing

Abstract

A simple algorithm is presented which minimizes the mean testing time for VLSI circuits. By breaking up the testing process into subintervals, and analyzing the signature at the end of each subinterval, it is possible to abort future tests if the circuit is found to be faulty, thus saving test time. Subdivision of the test process also reduces the probability of aliasing, thus increasing the effective coverage of the signature analysis process. Also, if the process is sufficiently subdivided, it may be possible to use the test results not only to determine if the circuit is faulty or not, but to diagnose the fault.