Performance Evaluation of a Decoded Instruction Cache for Variable Instruction Length Computers

Abstract

A Decoded INstruction Cache (DINC) is a buffer between the instruction decoder and other instruction pipeline stages. In this paper, we explain how techniques that reduce the branch penalty on a DINC, can improve CPU performance. We also analyze the impact of some of the design parameters of DINC's on variable instruction length computers. Our study indicates that tuning the mapping of the instructions into the cache can improve performance substantially. Tuning must be based on the instruction length distribution for a specific architecture. In addition, the associativity degree has a greater effect on the DINC's performance than on the performance of regular caches. We discuss the difference between the performance of DINC's and other caches, when longer cache lines are used. We present a model to estimate the miss rate based on its characteristics, that were discussed and analyzed throughout this paper. Our conclusions are based on both analytical study and trace driven simulations of several integer UNIX™ applications. © 1994 IEEE